Traditionally, EPROMs and EEPROMs have been implemented using a non-planar FAMOS technology. The non-planar technology has several inherent problems which can be solved by the use of a planar technology. U.S. Pat. No. 4,597,060 to Mitchell describes a method of forming a FAMOS cell which is planarized.
The planar technology provides for a small memory cell, which is more reliable and which has enhanced programming capabilities. Despite the superior qualities of the planar FAMOS transistor, a programming voltage of 12.5 volts is still necessary for reliable programming. In order to reduce the magnitude of the electric fields created during programming, it is desirable that the programming voltage be reduced. Preferably, the programming voltage should approach five volts.
Therefore, a need has arisen for a planar and non-planar FAMOS technology for use in EPROMs, EEPROMs, EPALs, and other devices using similar memory structures, in which the programming voltage is reduced, and the reliability of the devices increased.